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general description the max1449 3.3v, 10-bit analog-to-digital converter(adc) features a fully differential input, a pipelined 10- stage adc architecture with wideband track-and-hold (t/h), and digital error correction incorporating a fully dif- ferential signal path. the adc is optimized for low- power, high-dynamic performance in imaging and digital communications applications. the converter operates from a single 2.7v to 3.6v supply, consuming only 186mw while delivering a 58.5db (typ) signal-to-noise ratio (snr) at a 20mhz input frequency. the fully differ- ential input stage has a -3db 400mhz bandwidth and may be operated with single-ended inputs. in addition to low operating power, the max1449 features a 5a power-down mode for idle periods. an internal 2.048v precision bandgap reference is used to set the adc? full-scale range. a flexible refer- ence structure allow? the user to supply a buffered, direct, or externally derived reference for applications requiring increased accuracy or a different input volt- age range. lower speed, pin-compatible versions of the max1449 are also available. refer to the max1444 data sheet for a 40msps version, the max1446 data sheet for a 60msps version, and the max1448 data sheet for 80msps. the max1449 has parallel, offset binary, cmos-com- patible, three-state outputs that can be operated from 1.7v to 3.6v to allow flexible interfacing. the device is available in a 5mm x 5mm 32-pin tqfp package and is specified over the extended industrial (-40? to +85?) temperature range. ________________________applications ultrasound imagingccd imaging baseband and if digitization digital set-top boxes video digitizing applications features ? single 3.3v operation ? excellent dynamic performance 58.5db snr at f in = 20mhz 72dbc sfdr at f in = 20mhz ? low power 62ma (normal operation)5a (shutdown mode) ? fully differential analog input ? wide 2vp-p differential input voltage range ? 400mhz -3db input bandwidth ? on-chip 2.048v precision bandgap reference ? cmos-compatible three-state outputs ? 32-pin tqfp package ? evaluation kit available (max1448 ev kit) max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference ________________________________________________________________ maxim integrated products 1 clk in+ control 10 pipeline adc ref system + bias output drivers d e c ref refin refout refp com refn oe v dd gndov dd ognd d9?0 in- pd t/h max1449 functional diagram 19-4802; rev 2; 9/04 evaluation kit available ordering information pin configuration appears at end of data sheet. part temp range pin-package MAX1449EHJ -40 c to +85 c 32 tqfp part sampling speed (msps) max1444 40 max1446 60 max1448 80 pin-compatible, lower speed selection table for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v dd = 3.3v, ov dd = 2v, 0.1? and 1? capacitors from refp, refn, and com to gnd, v refin = 2.048v, refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs, f clk = 105mhz, t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization; typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , ov dd to gnd ...............................................-0.3v to +3.6v ognd to gnd.......................................................-0.3v to +0.3v in+, in- to gnd........................................................-0.3v to v dd refin, refout, refp, refn, and com to gnd........................-0.3v to (v dd + 0.3v) oe , pd, clk to gnd..................................-0.3v to (v dd + 0.3v) d9?0 to gnd.........................................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70?) 32-pin tqfp (derate 18.7mw/? above +70?).....1495.3mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range ............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity inl f in = 7.5mhz, t a +25? 0.75 ?.4 lsb differential nonlinearity dnl f in = 7.5mhz, no missing codes guaranteed, t a +25? 0.5 1.0 lsb offset error < 1 1.7 % fs gain error t a +25?, t a +25? 0 2 % fs analog input input differential range v diff differential or single-ended inputs 1.0 v common-modevoltage range v com v dd /2 0.5 v input resistance r in switched capacitor load 20 k input capacitance c in 5p f conversion rate maximum clock frequency f clk 105 mhz data latency 5.5 cycles dynamic characteristics (f clk = 105.26mhz, 4096-point fft) f in = 7.5mhz 55.9 58.5 f in = 20mhz 55.5 58.5 signal-to-noise ratio(note 1) snr f in = 50mhz 58 db f in = 7.5mhz 55.3 58.2 f in = 20mhz 54.5 58.1 signal-to-noise + distortion (upto 5th harmonic) (note 1) sinad f in = 50mhz 57.6 db f in = 7.5mhz 62 72 f in = 20mhz 61 72 spurious-free dynamicrange (note 1) sfdr f in = 50mhz 70 dbc downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units f in = 7.5mhz -72 f in = 20mhz -72 third-harmonic distortion(note 1) hd3 f in = 50mhz -70 dbc intermodulation distortion (first 5odd-order imds) (note 2) imd f 1 = 38mhz at -6.5db fs f 2 = 42mhz at -6.5db fs -76 dbc third-order intermodulationdistortion (note 2) im3 f 1 = 38mhz at -6.5db fs f 2 = 42mhz at -6.5db fs -76 dbc f in = 7.5mhz -70 -62 f in = 20mhz -70 -60 total harmonic distortion(first 5 harmonics) (note 1) thd f in = 50mhz -70 dbc small-signal bandwidth input at -20db fs, differential inputs 500 mhz full-power bandwidth fpbw input at -0.5db fs, differential inputs 400 mhz aperture delay t ad 1n s aperture jitter t aj 2 ps rms overdrive recovery time for 1.5 x full-scale input 2 ns differential gain 1% differential phase 0.25 degrees output noise in+ = in- = com 0.2 ls b rm s internal reference reference output voltage refout 2.048 1% v reference temperaturecoefficient tc ref 60 ppm/ c load regulation 1.25 mv/ma buffered external reference (v refin = 2.048v) refin input voltage 2.048 positive reference outputvoltage 2.012 v negative reference outputvoltage 0.988 v common-mode level v dd / 2 v differential reference outputvoltage range v refin ? v ref = v refp - v refn , t a +25 c 0.98 1.024 1.07 v refin resistance v refp >50 m electrical characteristics (continued)(v dd = 3.3v, ov dd = 2v, 0.1? and 1? capacitors from refp, refn, and com to gnd, v refin = 2.048v, refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs, f clk = 105mhz, t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization; typical values are at t a = +25?.) downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units maximum refp, com sourcecurrent v refn 5m a maximum refp, com sinkcurrent v com -250 ? maximum refn source current i source 250 ? maximum refn sink current i sink -5 ma unbuffered external reference (v refin = agnd, reference voltage applied to refp, refn, and com) refp, refn input resistance r refp , r refn measured between refp and com andrefn and com 4k refp, refn, com inputcapacitance c in 15 pf differential reference inputvoltage range ? v ref ? v ref = v refp - v refn 1.024 10% v com input voltage range v com v dd / 2 10% v refp input voltage v refp v com + ? v ref / 2 v refn input voltage v refn v com - ? v ref / 2 v digital inputs (clk, pd, oe ) clk 0.8 x v dd input high threshold v ih pd, oe 0.8 x v dd v clk 0.2 x v dd input low threshold v il pd, oe 0.2 x v dd v input hysteresis v hyst 0.1 v i ih v ih = v dd = ov dd 5 a input leakage i il v il = 0 5 input capacitance c in 5p f electrical characteristics (continued)(v dd = 3.3v, ov dd = 2v, 0.1? and 1? capacitors from refp, refn, and com to gnd, v refin = 2.048v, refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs, f clk = 105mhz, t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization; typical values are at t a = +25?.) downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference _______________________________________________________________________________________ 5 note 1: snr, sinad, thd, sfdr, and hd3 are based on an analog input voltage of -0.5db fs referenced to a 1.024v full-scaleinput voltage range. note 2: intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. this number i s 6db better if referenced to the two-tone envelope. note 3: digital outputs settle to v ih ,v il . note 4: with refin driven externally, refp, com, and refn are left floating while powered down. parameter symbol conditions min typ max units digital outputs (d9Cd0) output voltage low v ol i sink = 200? 0.2 v output voltage high v oh i source = 200? ov dd - 0.2 v three-state leakage current i leak oe = ov dd 10 ? three-state output capacitance c out oe = ov dd 5p f power requirements analog supply voltage v dd 2.7 3.3 3.6 v output supply voltage ov dd 1.7 3.3 3.6 v operating, f in = 20mhz at -0.5db fs 58 74 ma analog supply current i vdd shutdown, clock idle, pd = oe = ov dd 41 5 a operating, c l = 15pf , f in = 20mhz at -0.5db fs 10 ma output supply current i ovdd shutdown, clock idle, pd = oe = ov dd 12 0 a offset 0.1 mv/v power supply rejection psrr gain 0.1 %/v timing characteristics clk rise-to-output data valid t do figure 6 (note 3) 5 8 ns oe fall-to-output enable t enable figure 5 10 ns oe rise-to-output disable t disable figure 5 15 ns clk pulse width high t ch figure 6, clock period 9.52ns 4.76 ?.47 ns clk pulse width low t cl figure 6, clock period 9.52ns 4.76 ?.47 ns wake-up time t wake (note 4) 1.5 ? electrical characteristics (continued)(v dd = 3.3v, ov dd = 2v, 0.1? and 1? capacitors from refp, refn, and com to gnd, v refin = 2.048v, refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs, f clk = 105mhz, t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization; typical values are at t a = +25?.) downloaded from: http:///
t ypical operating characteristics (v dd = 3.3v, ov dd = 2.0v, internal reference, differential input at -0.5db fs, f clk = 106.2345mhz, c l 10pf, t a = +25?, unless otherwise noted.) -100 -70-80 -90 -60 -50 -40 -30 -20 -10 0 02 0 10 30 40 50 60 fft plot (f in = 7.5mhz, 8192-point fft, differential input) max1449 toc01 analog input frequency (mhz) amplitude (db) snr = 58.6dbsinad = 58.4db thd = -72.7dbc sfdr = 73.6dbc 2nd harmonic 3rd harmonic -100 -70-80 -90 -60 -50 -40 -30 -20 -10 0 02 0 10 30 40 50 60 max1449 toc02 fft plot (f in = 19.99mhz, 8192-point fft, differential input) analog input frequency (mhz) amplitude (db) snr = 58.5dbsinad = 58.4db thd = -73.7dbc sfdr = 75.9dbc 2nd harmonic 3rd harmonic -100 -70-80 -90 -60 -50 -40 -30 -20 -10 0 02 0 10 30 40 50 60 max1449 toc03 fft plot (f in = 50.12mhz, 8192-point fft, differential input) analog input frequency (mhz) amplitude (db) snr = 57.9dbsinad = 56.7db thd = -71.3dbc sfdr = 71.1dbc 2nd harmonic 3rd harmonic -100 -70-80 -90 -60 -50 -40 -30 -20 -10 0 02 0 10 30 40 50 60 max1449 toc04 fft plot (f in = 7.5mhz, 8192-point fft, single-ended input) analog input frequency (mhz) amplitude (db) snr = 57.7dbsinad = 57.5db thd = -71.8dbc sfdr = 74.4dbc 2nd harmonic 3rd harmonic -100 -70-80 -90 -60 -50 -40 -30 -20 -10 0 02 0 10 30 40 50 60 max1449 toc05 fft plot (f in = 19.99mhz, 8192-point fft, single-ended input) analog input frequency (mhz) amplitude (db) snr = 57.7dbsinad = 57.2db thd = -67dbc sfdr = 67.7dbc 2nd harmonic 3rd harmonic -100 -70-80 -90 -60 -50 -40 -30 -20 -10 0 02 0 10 30 40 50 60 max1449 toc06 two-tone intermodulation (8192-point imd, differential input) analog input frequency (mhz) amplitude (db) f 1 = 38mhz at -6.5db fs f 2 = 42mhz at -6.5db fs 2nd-order imd 3rd-order imd f 1 f 2 8050 11 0 100 spurious-free dynamic range vs. analog input frequency 56 max1449 toc07 analog input frequency (mhz) sfdr (dbc) 62 68 74 differential single ended 6050 11 01 0 0 signal-to-noise ratio vs. analog input frequency 52 max1449 toc08 analog input frequency (mhz) snr (db) 54 56 58 differential single ended thd (dbc) -50-80 11 0 100 total harmonic distortion vs. analog input frequency -74 max1449 toc09 analog input frequency (mhz) -68 -62 -56 differential single ended max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference 6 _______________________________________________________________________________________ downloaded from: http:///
sinad (db) 6050 11 0 100 signal-t0-noise + distortion vs. analog input frequency 52 max1449 toc10 analog input frequency (mhz) 54 56 58 differential single-ended -8 1 1000 100 10 full-power input bandwidth vs. analog input frequency, single ended 60 -6 4 2 max1449 toc11 analog input frequency (mhz) amplitude (db) -2 -4 -8 11 0 0 0 100 10 small-signal input bandwidth vs. analog input frequency, single ended 60 -6 4 2 max1449 toc12 analog input frequency (mhz) u(d) -2 -4 v in = 100mvp-p 50 6055 7065 75 80 -12 -6 -9 -3 0 spurious-free dynamic range vs. analog input power (f in = 19mhz) max1449 toc13 analog input power (db fs) sfdr (dbc) 40 45 5550 60 65 signal-to-noise ratio vs. analog input power (f in = 19mhz) max1449 toc14 analog input power (db fs) snr (db) -12 -6 -9 -3 0 -80 -70-75 -60-65 -55 -12 -6 -9 -3 0 total harmonic distortion vs. analog input power (f in = 19mhz) max1449 toc15 analog input power (db fs) thd (dbc) -50 40 45 5550 60 65 signal-to-noise + distortion vs. analog input power (f in = 19mhz) max1449 toc16 analog input power (db fs) sinad (db) -12 -6 -9 -3 0 64 68 7672 80 84 -40 10 -15 35 60 85 spurious-free dynamic range vs. temperature max1449 toc17 temperature ( c) sfdr (dbc) f in = 26.1696mhz 50 54 6258 66 70 -40 10 -15 35 60 85 signal-to-noise vs. temperature max1449 toc18 temperature ( c) snr (db) f in = 26.1696mhz t ypical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, internal reference, differential input at -0.5db fs, f clk = 106.2345mhz, c l 10pf, t a = +25?, unless otherwise noted.) max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference _______________________________________________________________________________________ 7 downloaded from: http:///
-80 -76 -68-72 -64 -60 -40 10 -15 35 60 85 total harmonic distortion vs. temperature max1449 toc19 temperature ( c) thd (dbc) f in = 26.1696mhz 50 54 6258 66 70 -40 10 -15 35 60 85 signal-to-noise + distortion vs. temperature max1449 toc20 temperature ( c) sinad (db) f in = 26.1696mhz -0.4 -0.2-0.3 0.1 0 -0.1 0.40.3 0.2 0.5 0 400 200 600 800 1000 1200 integral nonlinearity vs. digital output code (best straight line) max1449 toc21 digital output code inl (lsb) -0.4 -0.2-0.3 0.1 0 -0.1 0.40.3 0.2 0.5 0 400 200 600 800 1000 1200 differential nonlinearity vs. digital output code max1449 toc22 digital output code dnl (lsb) 0 0.02 0.060.04 0.08 0.10 -40 10 -15 35 60 85 gain error vs. temperature, external reference, v refin = +2.048v max1449 toc23 temperature ( c) gain error (lsb) -2 0 -1 21 3 4 -40 10 -15 35 6 08 5 offset error vs. temperature, external reference, v refin = +2.048v max1449 toc24 temperature ( c) offset error (lsb) 40 5045 6055 65 70 -40 10 -15 35 6 08 5 analog supply current vs. temperature max1449 toc26 temperature ( c) i vdd (ma) 0 3 96 12 15 -40 10 -15 35 60 85 digital supply current vs. temperature max1449 toc27 temperature ( c) i ovdd (ma) 51 5553 5957 61 63 2.70 3.00 3.15 2.85 3.30 3.45 3.60 analog supply current vs. analog supply voltage max1449 toc25 v dd (v) i vdd (ma) t ypical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, internal reference, differential input at -0.5db fs, f clk = 106.2345mhz, c l 10pf, t a = +25?, unless otherwise noted.) max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference 8 _______________________________________________________________________________________ downloaded from: http:///
1210 86 4 -40 10 -15 35 6 08 5 digital supply current vs. temperature max1449 toc28 temperature ( c) i ovdd (ma) 2.00 2.20 2.602.40 2.80 3.00 2.70 3.00 2.85 3.15 3.30 3.45 3.60 analog power-down current vs. analog supply voltage max1449 toc29 v dd (v) i vdd ( a) 12 96 3 0 2.0 2.6 2.3 3.0 3.3 3.6 digital power-down current vs. digital supply voltage max1449 toc30 ov dd (v) i ovdd ( a) 50 6055 7065 75 80 100 108 104 112 116 120 snr/sinad, thd/sfdr vs. clock frequency max1449 toc31 clock frequency (mhz) snr/sinad, thd/sfdr (db, dbc) f in = 50.123mhz sfdr snr sinad thd 2.1002.075 2.050 2.025 2.000 2.70 3.15 2.85 3.00 3.30 3.45 3.60 internal reference voltage vs. analog supply voltage max1449 toc32 v dd (v) v refout (v) 2.00 2.02 2.062.04 2.08 2.10 -40 10 -15 35 60 85 internal reference voltage vs. temperature max1449 toc33 temperature ( c) v refout (v) 0 20,00010,000 40,00030,000 60,00050,000 70,000 n-2 n n-1 n+1 n+2 output noise histogram (dc input) max1449 toc34 digital output code counts 0 607 64676 252 0 t ypical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, internal reference, differential input at -0.5db fs, f clk = 106.2345mhz, c l 10pf, t a = +25?, unless otherwise noted.) max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference _______________________________________________________________________________________ 9 downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference 10 ______________________________________________________________________________________ pin description pin name function 1 refn lower reference. conversion range is (v refp - v refn ). bypass to gnd with a > 0.1? capacitor. 2 com common-mode voltage output. bypass to gnd with a > 0.1? capacitor. 3, 9, 10 v dd analog supply voltage. bypass to gnd with a capacitor combination of 2.2? in parallel with 0.1?. 4, 5, 8, 11, 14, 30 gnd analog ground 6 in+ positive analog input. for single-ended operation connect signal source to in+. 7 in- negative analog input. for single-ended operation connect in- to com. 12 clk conversion clock input 13 pd power down input.high: power-down mode low: normal operation 15 oe output enable input.high: digital outputs disabled low: digital outputs enabled 16?0 d9?5 three-state digital outputs d9?5. d9 is the msb. 21 ov dd output driver supply voltage. bypass to gnd with a capacitor combination of 2.2? in parallel with0.1?. 22 t.p. test point. do not connect. 23 ognd output driver ground 24?8 d4?0 three-state digital outputs d4?0. d0 is the lsb. 29 refout internal reference voltage output. may be connected to refin through a resistor or a resistor-divider. 31 refin reference input. v refin = 2 x (v refp - v refn ). bypass to gnd with a > 0.1? capacitor. 32 refp upper reference. conversion range is (v refp - v refn ). bypass to gnd with a > 0.1? capacitor. downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference ______________________________________________________________________________________ 11 detailed description the max1449 uses a 10-stage, fully differential,pipelined architecture (figure 1), that allows for high- speed conversion while minimizing power consump- tion. each sample moves through a pipeline stage every half-clock cycle. counting the delay through the output latch, the clock-cycle latency is 5.5. a 1.5-bit (2-comparator) flash adc converts the held input voltage into a digital code. the following digital- to-analog converter (dac) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. the resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all 10 stages. each stage provides a 1- bit resolution. digital error-correction compensates for adc comparator offsets in each pipeline stage and ensures no missing codes. input track-and-hold (t/h) circuit figure 2 displays a simplified functional diagram of the input track-and-hold (t/h) circuit in both track and hold mode. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential circuit samples the input signal onto the two capacitors c2a and c2b through switches s4a and s4b. switches s2a and s2b set the common mode for the amplifier input, and open simultaneously with s1, sampling the inputwaveform. switches s4a and s4b are then opened before switches s3a and s3b connect capacitors c1a and c1b to the output of the amplifier and switch s4c is closed. the resulting differential voltage is held on capacitors c2a and c2b. the amplifier is used to charge capacitors c1a and c1b to the same values originally held on c2a and c2b. this value is then pre- sented to the first stage quantizer and isolates the pipeline from the fast-changing input. the wide input bandwidth t/h amplifier allows the max1449 to track and sample/hold analog inputs of high frequencies beyond nyquist. the analog inputs in+ and in- can be driven either differentially or single-ended. it is recom- mended to match the impedance of in+ and in- and set the common-mode voltage to mid-supply (v dd /2) for optimum performance. analog input and reference configuration the full-scale range of the max1449 is determined by theinternally generated voltage difference between refp (v dd /2 + v refin /4) and refn (v dd /2 - v refin /4). the adc? full-scale range is user-adjustable through therefin pin, which provides a high input impedance for this purpose. refout, refp, com (v dd /2), and refn are internally buffered low-impedance outputs. t/h v out x2 flash adc dac 1.5 bits mdac 10 v in v in stage 1 stage 2 d9?0 v in = input voltage between in+ and in- (differential or single ended) digital correction logic stage 10 figure 1. pipelined architecture?tage blocks s3b s3a com s5b s2b s5a in+in- s1 outout c2ac2b s4c s4a s4b c1b c1a internal bias internal bias com track track clk internalnonoverlapping clock signals hold hold s2a figure 2. internal t/h circuit downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference 12 ______________________________________________________________________________________ the max1449 provides three modes of reference oper-ation: ? nternal reference mode buffered external reference mode unbuffered external reference mode in internal reference mode, the internal reference out- put refout can be tied to the refin pin through a resistor (e.g., 10k ? ) or resistor-divider, if an application requires a reduced full-scale range. for stability pur-poses it is recommended to bypass refin with a >10nf capacitor to gnd. in buffered external reference mode, the reference volt- age levels can be adjusted externally by applying a stable and accurate voltage at refin. in this mode, refout may be left open or connected to refin through a >10k ? resistor. in unbuffered external reference mode, refin is con- nected to gnd thereby deactivating the on-chip buffers of refp, com, and refn. with their buffers shut down, these pins become high impedance and can be driven by external reference sources. clock input (clk) the max1449? clk input accepts cmos-compatibleclock signals. since the inter-stage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). in particular, sampling occurs on the falling edge of the clock signal, mandating this edge to provide lowest possible jitter. any significant aperture jitter would limit the snr per- formance of the adc as follows: where f in represents the analog input frequency and t aj is the time of the aperture jitter. clock jitter is especially critical for undersamplingapplications. the clock input should always be consid- ered as an analog input and routed away from any ana- log input or other digital signal lines. the max1449 clock input operates with a voltage threshold set to v dd /2. clock inputs with a duty cycle other than 50% must meet the specifications for highand low periods as stated in the electrical characteristics . (see figures 3 (3a, 3b) and 4 (4a, 4b) for the relationship between spurious-free dynamicrange (sfdr), signal-to-noise ratio (snr), total harmon- ic distortion (thd), or signal-to-noise plus distortion (sinad) vs. duty cycle.) output enable ( o o e e ), power down (pd), and output data (d0?9) all data outputs, d0 (lsb) through d9 (msb), arettl/cmos logic-compatible. there is a 5.5 clock-cycle latency between any particular sample and its valid output data. the output coding is straight offset binary (table 1). with oe and pd high, the digital outputs enter a high-impedance state. if oe is held low with pd high, the outputs are latched at the last value prior tothe power down. the capacitive load on the digital outputs d0 through d9 should be kept as low as possible (<15pf), to avoid large digital currents that could feed back into the ana- log portion of the max1449, thereby degrading its dynamic performance. the use of buffers on the digital outputs of the adc can further isolate the digital outputs from heavy capacitive loads. to further improve the dynamic performance of the max1449, small series resistors (e.g., 100 ? ) may be added to the digital output paths, close to the adc. figure 5 displays the timingrelationship between output enable and data output valid as well as power-down/wake-up and data output valid. snr ft in aj = ? ? ? ? ? ? 20 1 2 log table 1. max1449 output code for differential inputs differential input voltage* differential input straight offset binary v ref 511/512 +full scale -1lsb 11 1111 1111 v ref 510/512 +full scale -2lsb 11 1111 1110 v ref 1/512 +1lsb 10 0000 0001 0 bipolar zero 10 0000 0000 - v ref 1/512 -1lsb 01 1111 1111 - v ref 511/512 negative full scale + 1lsb 00 0000 0001 - v ref 512/512 negative full scale 00 0000 0000 * v ref = v refp = v refn downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference ______________________________________________________________________________________ 13 50 58 7466 82 90 35 49 42 56 63 70 clock duty cycle (%) sfdr (dbc) f in = 25.123mhz at -0.5db fs figure 3a. spurious free dynamic range vs. clock duty cycle(differential input) 54 5756 55 6058 59 61 62 35 49 42 56 63 70 clock duty cycle (%) snr (db) f in = 25.123mhz at -0.5db fs figure 3b. signal-to-noise ratio vs. clock duty cycle(differential input) -85 -75-80 -65-70 -55-60 -50 35 49 42 56 63 70 clock duty cycle (%) thd (dbc) f in = 25.123mhz at -0.5db fs figure 4a. total harmonic distortion vs. clock duty cycle(differential input) 52 5654 6058 62 64 35 49 42 56 63 70 clock duty cycle (%) sinad (db) f in = 25.123mhz at -0.5db fs figure 4b. signal-to-noise plus distortion vs. clock duty cycle(differential input) output data d9?0 oe t disable t enable high-z high-z valid data figure 5. output enable timing downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference 14 ______________________________________________________________________________________ system timing requirements figure 6 depicts the relationship between the clockinput, analog input, and data output. the max1449 samples at the falling edge of the input clock. output data is valid on the rising edge of the input clock. the output data has an internal latency of 5.5 clock cycles. figure 6 also determines the relationship between the input clock parameters and the valid output data. applications information figure 7 depicts a typical application circuit containing a single-ended to differential converter. the internal refer- ence provides a v dd /2 output voltage for level shifting purposes. the input is buffered and then split to a volt- age follower and inverter. a low-pass filter, to suppress some of the wideband noise associated with high-speed op amps, follows the op amps. the user may select the r iso and c in values to optimize the filter performance, to suit a particular application. for the application in figure7, a r iso of 50 ? is placed before the capacitive load to prevent ringing and oscillation. the 22pf c in capacitor acts as a small bypassing capacitor. using transformer coupling an rf transformer (figure 8) provides an excellentsolution to convert a single-ended source signal to a fully differential signal, required by the max1449 for optimum performance. connecting the center tap of the transformer to com provides a v dd /2 dc level shift to the input. although a 1:1 transformer is shown, a step-up transformer may be selected to reduce the drive requirements. a reduced signal swing from the input driver, such as an op amp, may also improve the over- all distortion. in general, the max1449 provides better sfdr and thd with fully differential input signals than single- ended drive, especially for very high input frequencies. in differential input mode, even-order harmonics are lower as both inputs (in+, in-) are balanced, and each of the inputs only requires half the signal swing com- pared to single-ended mode. single-ended ac-coupled input signal figure 9 shows an ac-coupled, single-ended applica-tion. the max4108 op amp provides high speed, high bandwidth, low-noise, and low-distortion to maintain the integrity of the input signal. n - 6 n n - 5 n + 1 n - 4 n + 2 n - 3 n + 3 n - 2 n + 4 n - 1 n + 5 n n + 6 n + 1 5.5 clock-cycle latency analog inputclock input data output t d0 t ch t cl figure 6. system and output timing diagram downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference ______________________________________________________________________________________ 15 input 300 ? -5v 5v 0.1 f 0.1 f 0.1 f c in 22pf c in 22pf r iso 50 ? r iso 50 ? -5v 600 ? 300 ? 300 ? in+in- lowpass filter com 600 ? 5v -5v 0.1 f 600 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f 5v 0.1 f 300 ? max4108 max1449 max4108 max4108 lowpass filter figure 7. typical application circuit using the internal reference max1449 t1 n.c. v in 4 3 2 5 6 1 22pf 22pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? mini-circuits adt1-1wt in- in+ com figure 8. using a transformer for ac-coupling max1449 0.1 f 1k ? 1k ? 100 ? 100 ? c in com c in in+in- 0.1 f r iso r iso refp refn r iso = 50 ? c in = 22pf v in max4108 figure 9. single-ended ac-coupled input downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference 16 ______________________________________________________________________________________ buffered external reference drives multiple adcs multiple-converter systems based on the max1449 arewell suited for use with a common reference voltage. the refin pin of those converters can be connected directly to an external reference source. a precision bandgap reference like the max6062 generates an external dc level of 2.048v (figure 10), and exhibits a noise voltage density of 150nv/ hz . its output passes through a 1-pole lowpass filter (with 10hz cutoff fre- quency) to the max4250, which buffers the referencebefore its output is applied to a second 10hz lowpass filter. the max4250 provides a low offset voltage (for high-gain accuracy) and a low noise level. the passive 10hz filter following the buffer attenuates noise pro- duced in the voltage reference and buffer stages. this filtered noise density, which decreases for higher fre- quencies, meets the noise levels specified for precision adc operation. refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f 0.1 f 2.048v 100 f 2 5 3 2 3 1 4 1 max1449 n = 1 max4250 refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f 0.1 f max1449 n = 1000 0.1 f 162 ? 16.2k ? 3.3v 1 f 10hz lowpass filter 10hz lowpass filter note: one front-end reference circuit design may be used with up to 1000 adcs. 2.2 f 10v 0.1 f 0.1 f 3.3v max6062 figure 10. buffered external reference drives up to 1000 adcs downloaded from: http:///
unbuffered external reference drives multiple adcs connecting each refin to analog ground disables theinternal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. followed by a 10hz lowpass filter and precision voltage-divider (figure 11), the max6066 gen- erates a dc level of 2.500v. the buffered outputs of this divider are set to 2.0v, 1.5v, and 1.0v, with an accuracy that depends on the tolerance of the divider resistors. the three voltages are buffered by the max4252, which pro- vides low noise and low dc offset. the individual voltage followers are connected to 10hz lowpass filters, which fil- ter both the reference voltage and amplifier noise to alevel of 3nv/ hz . the 2.0v and 1.0v reference voltages set the differential full-scale range of the associatedadcs at 2v p-p . the 2.0v and 1.0v buffers drive the adc? internal ladder resistances between them. notethat the common power supply for all active components removes any concern regarding power-supply sequenc- ing when powering up or down. with the outputs of the max4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 adcs. for applications that require more than 32 matched adcs, a voltage reference and divider string common to all converters is highly recommended. max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference ______________________________________________________________________________________ 17 refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f 330 f 6v 330 f 6v 330 f 6v 10 f 6v 11 4 3 2 3 1 2 1 max1449 n = 1 max6066 1/4 max4252 refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f max1449 n = 32 47 ? 2.0v at 8ma 1.47k ? 21.5k ? 3.3v 1 f 21.5k ? 21.5k ? 21.5k ? 21.5k ? note: one front-end reference circuit design may be used with up to 32 adcs. 2.2 f 10v 0.1 f 0.1 f 3.3v 2.0v 10 f 6v 11 4 5 6 7 1/4 max4252 47 ? 1.5v at 0ma 1.47k ? 3.3v 10 f 6v 11 4 10 9 8 1/4 max4252 47 ? 1.0v at -8ma 1.47k ? 3.3v 3.3v max4254 power-supply bypassing.place capacitor as close as possible to the op amp. 0.1 f 1.5v 1.0v figure 11. unbuffered external reference drives up to 32 adcs downloaded from: http:///
max1449 grounding, bypassing, and board layout the max1449 requires high-speed board layout designtechniques. locate all bypass capacitors as close to the device as possible, preferably on the same side as the adc, using surface mount devices for minimum inductance. bypass v dd , refp, refn, and com with two parallel 0.1? ceramic capacitors and a 2.2? bipolar capacitor to gnd. follow the same rules to bypass the digital supply (ov dd ) to ognd. multi-layer boards with separated ground and power planes pro-duce the highest level of signal integrity. consider the use of a split ground plane arranged to match the physical location of the analog ground (gnd) and the digital output driver ground (ognd) on the adc's package. the two ground planes should be joined at a single point, such that the noisy digital ground currents do not interfere with the analog ground plane. the ideal location of this connection can be determined experi- mentally at a point along the gap between the two ground planes, which produces optimum results. make this connection with a low-value, surface-mount resistor (1 ? to 5 ? ), a ferrite bead or a direct short. alternatively, all ground pins could share the same ground plane, ifthe ground plane is sufficiently isolated from any noisy digital systems ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from sensitive analog traces. keep all signal lines short and free of 90 turns. static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on anactual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the max1449 are measured using the best straight-line fit method. differential nonlinearity (dnl) differential nonlinearity is the difference between anactual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. dynamic parameter definitions aperture jitter figure 12 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the falling-edge of the sampling clock and the instant whenan actual sample is taken (figure 12). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital sam- ples, the theoretical maximum snr is the ratio of the full- scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum ana- log-to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr (max) = 6.02 x n + 1.76 in reality, there are other noise sources besides quanti-zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig-nal to all spectral components minus the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc ata specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob is computed from: total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first fiveharmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. thd vvvv v = +++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log () enob sinad . . = ? () 176 602 10-bit, 105msps, single 3.3v, low-power adc with internal reference 18 ______________________________________________________________________________________ downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference ______________________________________________________________________________________ 19 spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rmsamplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest spurious component, excluding dc offset. intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels ofeither input tone to the worst 3rd-order (or higher) inter- modulation products. the individual input tone levels are at -6.5db full scale and their envelope is at -0.5db full scale. hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 12. t/h aperture timing pin configuration chip information transistor count: 5684process: cmos max1449 tqfp top view 32 28 29 30 31 25 26 27 refingnd refout d0 refpd1 d2 d3 10 13 15 14 16 11 12 9 v dd gnd v dd pd clk oe gnd d9 17 18 19 20 21 22 23 ognd 24 d4t.p. ov dd d5d6 d7 d8 2 3 4 5 6 7 8 gnd in- in+ gnd gnd v dd com 1 refn downloaded from: http:///
max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference 20 ______________________________________________________________________________________ 32l tqfp, 5x5x01.0.eps b 1 2 21-0110 package outline, 32l tqfp, 5x5x1.0mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) downloaded from: http:///
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 21 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. b 2 2 21-0110 package outline, 32l tqfp, 5x5x1.0mm max1449 10-bit, 105msps, single 3.3v, low-power adc with internal reference package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) downloaded from: http:///

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